1. Field of the Invention
The present invention relates in general to the field of signal processing, and more specifically to a power control system and method using a delta sigma modulator with unavailable intermediate output values.
2. Description of the Related Art
Power control systems often utilize a switching power converter to convert alternating current (AC) voltages to direct current (DC) voltages or DC-to-DC. Switching power converters often include a nonlinear energy transfer process to provide power factor corrected energy to a load. Power control systems often provide power factor corrected and regulated output voltages to many devices that utilize a regulated output voltage.
FIG. 1 represents a power control system 100, which includes a switching power converter 102. Voltage source 101 supplies an AC input voltage Vin to a full bridge diode rectifier 103. The voltage source 101 is, for example, a public utility, and the input voltage Vin is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The rectifier 103 rectifies the input voltage Vin and supplies a rectified, time-varying, line input voltage VX to the switching power converter 102.
The power control system 100 includes a PFC and output voltage controller 114 to control power factor correction and regulate an output voltage VC of switching power converter 102. The PFC and output voltage controller 114 controls an ON (i.e. conductive) and OFF (i.e. nonconductive) state of switch 108 by varying a state of pulse width modulated control signal CS0. Switching between states of switch 108 regulates the transfer of energy from the rectified line input voltage VX through inductor 110 to capacitor 106. The inductor current iL ramps ‘up’ when the switch 108 is ON. The inductor current iL ramps down when switch 108 is OFF and supplies current iL to recharge capacitor 106. The time period during which inductor current iL ramps down is commonly referred to as the “inductor flyback time”. During the inductor flyback time, diode 111 is forward biased. Diode 111 prevents reverse current flow into inductor 110 when switch 108 is OFF. In at least one embodiment, the switching power converter 102 operates in discontinuous current mode, i.e. the inductor current iL ramp up time plus the inductor flyback time is less than the period of the control signal CS0, which controls the conductivity of switch 108. When operating in continuous conduction mode, the inductor current iL ramp-up time plus the inductor flyback time equals the period of control signal CS0.
Inductor current iL is proportionate to the ‘on-time’ of switch 108, and the energy transferred to inductor 110 is proportionate to the ‘on-time’ squared. Thus, the energy transfer process is one embodiment of a nonlinear process. In at least one embodiment, control signal CS0 is a pulse width modulated signal, and the switch 108 is a field effect transistor (FET), such as an n-channel FET. Control signal CS0 is a gate voltage of switch 108, and switch 108 conducts when the pulse width of CS0 is high. Thus, the ‘on-time’ of switch 108 is determined by the pulse width of control signal CS0. Accordingly, the energy transferred to inductor 110 is proportionate to a square of the pulse width of control signal CS0.
Capacitor 106 supplies stored energy to load 112. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage VC, as established by PFC and output voltage controller 114. The output voltage VC remains substantially constant during constant load conditions. However, as load conditions change, the output voltage VC changes. The PFC and output voltage controller 114 responds to the changes in VC and adjusts the control signal CS0 to restore a substantially constant output voltage VC as quickly as possible. The switching power converter 102 includes a small capacitor 115 to filter any high frequency signals from the input voltage VX.
The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, PFC and output voltage controller 114 attempts to control the inductor current iL so that the average inductor current iL is linearly and directly related to the line input voltage VX. Prodić, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 22, No. 5, Sep. 2007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of PFC and output voltage controller 114.
In at least one embodiment, the values of the pulse width and duty cycle of control signal CSo depend on sensing two signals, namely, the input voltage VX and the capacitor voltage/output voltage VC. PFC and output voltage controller 114 receives the two voltage signals, the input voltage VX and the output voltage VC, via a wide bandwidth current loop 116 and a slower voltage loop 118. The input voltage VX is sensed from node 120 between the diode rectifier 103 and inductor 110. The output voltage VC is sensed from node 122 between diode 111 and load 112. The current loop 116 operates at a frequency fc that is sufficient to allow the PFC and output voltage controller 114 to respond to changes in the line input voltage VX and cause the inductor current iL to track the input voltage VX to provide power factor correction. The current loop frequency is generally set to a value between 20 kHz and 130 kHz. The voltage loop 118 operates at a much slower frequency fv, typically 10-20 Hz. By operating at 10-20 Hz, the voltage loop 118 functions as a low pass filter to filter an AC ripple component of the output voltage VC.
The PFC and output voltage controller 114 controls the pulse width (PW) and period (TT) of control signal CS0. Thus, PFC and output voltage controller 114 controls the nonlinear process of switching power converter 102 so that a desired amount of energy is transferred to capacitor 106. The desired amount of energy depends upon the voltage and current requirements of load 112. To regulate the amount of energy transferred and maintain a power factor close to one, PFC and output voltage controller 114 varies the period TT of control signal CS0 so that the input current iL tracks the changes in input voltage VX and holds the output voltage VC constant. Thus, as the input voltage VX increases, PFC and output voltage controller 114 increases the period TT of control signal CS0, and as the input voltage VX decreases, PFC and output voltage controller 114 decreases the period TT of control signal CS0. At the same time, the pulse width PW of control signal CS0 is adjusted to maintain a constant duty cycle (D) of control signal CS0, and, thus, hold the output voltage VC constant. In at least one embodiment, the PFC and output voltage controller 114 updates the control signal CS0 at a frequency much greater than the frequency of input voltage VX. The frequency of input voltage VX is generally 50-60 Hz. The frequency 1/TT of control signal CS0 is, for example, between 20 kHz and 130 kHz. Frequencies at or above 20 kHz avoid audio frequencies and frequencies at or below 130 kHz avoid significant switching inefficiencies while still maintaining good power factor, e.g. between 0.9 and 1, and an approximately constant output voltage VC.
Referring to FIG. 1, the pulse width of control signal CS0 varies over time. For example, when the power demand of load 112 is low, such as when load 112 is an idle or standby state, PFC and output voltage controller 114 controls the pulse width of control signal CS0 so that some of the pulses of control signal CS0 are very small. When the pulse width of control signal CS0 is small, switch 108 turns ON and OFF quickly causing a short ON time duration. However, turning the switch 108 ON for short durations can create a problem because short switching durations can be very inefficient. The inefficiency occurs because, for example, the ratio of the power required to turn switch 108 ON to the power transferred to load 112 decreases as the ON time of switch 108 decreases.